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Copper Grain Structure Influences Stress Around Scaled TSVs (Purdue, UCLA)

Purdue and UCLA study mechanical stress in advanced packaging through-silicon vias

By GPU Data Hub Desk · GPU Data Hub·Editorial standards··United States

Academic researchers from Purdue University and UCLA have investigated how copper grain structures affect residual stress around through-silicon vias. The technical study examined scaled three-micrometre via arrays subjected to high-temperature annealing. Understanding these mechanical stresses is critical for improving reliability in advanced 3D semiconductor packaging.

Original source

This summary was written by the GPU Data Hub desk from reporting published by Semiconductor Engineering on 28 Sept 2026, 18:02. Read the full article at the original publisher.

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