Simulations Pinpoint Leakage Pathway In GAAFETs (Sandia, Luxembourg)

Researchers from Sandia National Laboratories and the Luxembourg Institute of Science and Technology have published research detailing parasitic leakage routes within gate-all-around field-effect transistors. The study relied on predictive first-principles simulations to isolate unwanted sub-surface electrical paths in the advanced transistor geometry. Addressing these leakage behaviours will be critical as the global semiconductor industry transitions beyond FinFETs toward tighter nanoscale nodes.