Vertical DRAM Stacking Expands Thermal Design Space Beyond HBM-on-GPU (imec)
imec investigates vertical DRAM configurations to mitigate processor thermal constraints
Research institute imec has analysed a novel three-dimensional memory layout that positions vertically oriented DRAM dies directly over a graphics processor. Thermal simulations indicate that integrating cooling channels within the structure provides a viable alternative to standard high-bandwidth memory packaging. The work evaluates how stack dimensions and memory density influence overall heat dissipation.
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This summary was written by the GPU Data Hub desk from reporting published by Semiconductor Engineering on 26 Oct 2026, 07:02. Read the full article at the original publisher.
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