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Advanced Packaging, HBM and CoWoS: How AI Chips Are Built
Modern AI accelerators are not a single piece of silicon. They combine compute dies with stacks of high-bandwidth memory using advanced packaging, and packaging capacity has become a key bottleneck for accelerator supply.
HBM: high-bandwidth memory
HBM stacks multiple DRAM dies vertically and places them next to the processor, giving far higher bandwidth than conventional memory. Each generation (HBM3, HBM3e and beyond) raises capacity and bandwidth.
TSVs and stacking
Through-silicon vias (TSVs) are vertical electrical connections that pass through a silicon die, allowing dies to be stacked and connected. They are fundamental to HBM.
CoWoS and 2.5D integration
CoWoS (chip-on-wafer-on-substrate) is TSMC's family of 2.5D packaging technologies that place compute dies and HBM stacks side by side on a silicon interposer. Many leading AI accelerators rely on it, which is why CoWoS capacity expansions are closely watched.
Frequently asked questions
Why is advanced packaging a bottleneck for AI chips?
Accelerators need compute dies and HBM integrated on specialised packages. Capacity for these packages and for HBM itself has been tighter than capacity for the underlying wafers.
What is the difference between 2.5D and 3D packaging?
2.5D places dies side by side on an interposer; 3D stacks dies vertically. HBM is itself a 3D stack, often combined with a processor in a 2.5D package.
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“Advanced Packaging, HBM and CoWoS: How AI Chips Are Built.” GPU Data Hub. https://gpudatahub.com/topics/semiconductor-advanced-packaging
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