Nanoelectromechanical Switches Target More Efficient Embedded DRAM (UC Berkeley, Samsung, Intel)

Joint research proposes hybrid switching to bypass conventional scaling limits

By GPU Data Hub Desk · GPU Data Hub·Editorial standards·18 Oct 2026, 23:28

Researchers from Samsung Electronics, Intel, and UC Berkeley have outlined an embedded dynamic memory architecture utilising nanoelectromechanical switches. The collaborative work seeks to overcome data retention limits and tackle persistent scaling barriers associated with legacy on-chip memory structures.

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This summary was written by the GPU Data Hub desk from reporting published by Semiconductor Engineering on 18 Oct 2026, 23:28. Read the full article at the original publisher.

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