AI COMPUTE•NVIDIA•GPU CLOUD•DATA CENTERS•SEMICONDUCTORS•ENERGY•FUNDING•M&A•AI COMPUTE•NVIDIA•GPU CLOUD•DATA CENTERS•SEMICONDUCTORS•ENERGY•FUNDING•M&A•
GPU·DATA HUB
Newsletter
Semiconductors

Stacked-Die Multi-Chip Architectures: The Tradeoff Between Scaling And Power Delivery

Integrated voltage regulators help resolve power delivery bottlenecks in 3D multi-chip designs

By GPU Data Hub Desk · GPU Data Hub·Editorial standards·
Stacked-Die Multi-Chip Architectures: The Tradeoff Between Scaling And Power Delivery

Managing efficient power delivery has emerged as a crucial hurdle in scaling multi-chip designs that utilise three-dimensional die stacking. Implementing integrated voltage regulators helps alleviate current density pressures and provides broader regulation bandwidth while minimising reliance on bulky external decoupling capacitor networks.

Original source

This summary was written by the GPU Data Hub desk from reporting published by Semiconductor Engineering on 22 Oct 2026, 07:02. Read the full article at the original publisher.

Read Original Source →

By subscribing you consent to receive the daily briefing. Unsubscribe at any time. See our privacy policy.

LinkedInX

More from GPU Data Hub

Latest →

PVTW: Extending Silicon Characterization From PVT To Real-World Workload

Conventional silicon characterisation methodologies based solely on process, voltage, and temperature parameters are expanding to incorporate active operational demands. Because identical devices can exhibit divergent behaviours under different software tasks, evaluation workflows are adopting workload-aware metrics to verify hardware performance.

Semiconductors··Semiconductor Engineering

Chip Scaling Moves Beyond The Transistor

Progress in semiconductor scaling is relying increasingly on system-level integration rather than traditional geometric transistor shrinkage. Ahead of future industry forums, developments across packaging architectures, optical interconnects, testing methods, and artificial intelligence are converging to shape device performance.

Semiconductors··Semiconductor Engineering

How Self-Aligned CFET Technology Could Extend CMOS Scaling Beyond 10 Å

Self-aligned complementary field-effect transistor schemes offer a manufacturing pathway to sustain CMOS scaling beyond the 10-ångström threshold. By expanding effective channel width and refining electrostatic control, this fabrication sequence aims to bolster performance across logic circuits and memory architectures.

Semiconductors··Semiconductor Engineering

What Breaks When Packaging Moves From Wafer To Panel?

Transitioning advanced packaging lines from standard round wafers to large-format rectangular panels is uncovering fundamental production challenges. Manufacturing engineers are discovering that baseline process assumptions fail on rectangular formats, necessitating new technical approaches to substrate handling and process control.

Semiconductors··Semiconductor Engineering