Randomized Caches in HW: Overheads And Limitations (RUB, Max Planck, Georgia Tech)

Researchers from Ruhr University Bochum, the Max Planck Institute, and Georgia Tech have assessed the practical trade-offs involved in implementing randomised caches in hardware. The technique mitigates side-channel security threats by masking the correlation between memory addresses and physical cache positions. The authors note that while previous proposals tackled architectural behaviour, physical hardware implementation obstacles have remained largely unaddressed.