AI COMPUTE•NVIDIA•GPU CLOUD•DATA CENTERS•SEMICONDUCTORS•ENERGY•FUNDING•M&A•AI COMPUTE•NVIDIA•GPU CLOUD•DATA CENTERS•SEMICONDUCTORS•ENERGY•FUNDING•M&A•
Semiconductors

AMD on track to overtake Intel as biggest x86 outfit

Chipmaker claims supply network is prepared for soaring server and AI demand

By GPU Data Hub Desk · GPU Data Hub·Editorial standards·
AMD on track to overtake Intel as biggest x86 outfit

Advanced Micro Devices is positioned to eclipse Intel as the dominant provider of x86 silicon, driven by accelerating enterprise demand for artificial intelligence workloads. The chipmaker's leadership confirmed that its supply chain infrastructure is equipped to manage the rapid influx of orders from data centres. The development marks a significant competitive milestone as server operators increasingly look beyond incumbent processor suppliers.

Original source

This summary was written by the GPU Data Hub desk from reporting published by The Register on 4 Nov 2026, 04:24. Read the full article at the original publisher.

Read Original Source →

By subscribing you consent to receive the daily briefing. Unsubscribe at any time. See our privacy policy.

LinkedInX

More from GPU Data Hub

Latest →

ARIA’s Scaling Inference Lab Deploys Lumai’s Optical Compute Tech

The UK's Advanced Research and Invention Agency will install Lumai's three-dimensional optical compute technology at its Scaling Inference Lab. Lumai uses light-based processing to conduct artificial intelligence inference, claiming up to a 90 per cent drop in data centre electricity consumption alongside 50-fold performance gains. The initiative forms part of state-backed research into next-generation processing platforms designed to curb infrastructure energy demands.

Semiconductors··HPCwire

Randomized Caches in HW: Overheads And Limitations (RUB, Max Planck, Georgia Tech)

Researchers from Ruhr University Bochum, the Max Planck Institute, and Georgia Tech have assessed the practical trade-offs involved in implementing randomised caches in hardware. The technique mitigates side-channel security threats by masking the correlation between memory addresses and physical cache positions. The authors note that while previous proposals tackled architectural behaviour, physical hardware implementation obstacles have remained largely unaddressed.

Semiconductors··Semiconductor Engineering