AI COMPUTE•NVIDIA•GPU CLOUD•DATA CENTERS•SEMICONDUCTORS•ENERGY•FUNDING•M&A•AI COMPUTE•NVIDIA•GPU CLOUD•DATA CENTERS•SEMICONDUCTORS•ENERGY•FUNDING•M&A•
GPU·DATA HUB
Newsletter
Semiconductors

Large-Format Masks Move From Aspiration To Industry Roadmap

Large-format photomasks transition to formal production roadmaps

By GPU Data Hub Desk · GPU Data Hub·Editorial standards·
Large-Format Masks Move From Aspiration To Industry Roadmap

Industry specialists have identified strong commercial and operational benefits in transitioning to large-format photomasks for semiconductor manufacturing. Realising these gains will require coordinated adaptation across the entire lithography supply chain. The format shift is consequently progressing from theoretical interest onto formal technology roadmaps.

Original source

This summary was written by the GPU Data Hub desk from reporting published by Semiconductor Engineering on 26 Oct 2026, 07:02. Read the full article at the original publisher.

Read Original Source →

By subscribing you consent to receive the daily briefing. Unsubscribe at any time. See our privacy policy.

LinkedInX

More from GPU Data Hub

Latest →

Testing Silicon Photonics At Scale

Volume manufacturing of silicon photonics is creating fresh demands for testing and measurement protocols. High-throughput production requires precise optical instrumentation, polarisation control, and accurate fibre coupling. Addressing these verification hurdles is becoming essential as optical technology expands across compute environments.

Semiconductors··Semiconductor Engineering

Bringing Down Test Costs For Co-Packaged Optics

The integration of optical engines into sophisticated packaging architectures is increasing the pressure to curb testing expenses. Manufacturers must reliably identify defects and guarantee component quality prior to final assembly to avoid costly package yield losses. Managing these validation workflows has become an essential priority for co-packaged optics commercialisation.

Semiconductors··Semiconductor Engineering

Self-Heating And Parasitics Challenge Multi-Tier CFET Scaling (TU Munich, IIT Kanpur)

Academics from the Technical University of Munich and IIT Kanpur have examined performance barriers facing multi-tier complementary field-effect transistors. Their study demonstrates that self-heating alongside parasitic interference from interconnect wiring presents major hurdles for vertically stacked nanosheet devices. These physical constraints could restrict the operational efficiency of future transistor architectures.

Semiconductors··Semiconductor Engineering

Pt-W Alloy Shows Potential For Thinner High-NA EUV Mask Absorbers (Chinese Academy of Sciences et al.)

Researchers at the Chinese Academy of Sciences and affiliated institutions have published technical work evaluating a platinum-tungsten alloy for high-NA extreme ultraviolet mask absorbers. The research suggests the alloy could allow for thinner absorber layers, supporting improved imaging performance during lithography. Advancements in absorber materials remain vital for scaling optical performance in future semiconductor fabrication nodes.

Semiconductors··Semiconductor Engineering

Dry-Deposited Resist Shows Different Tone Behavior Under EUV And E-Beam Exposure (KU Leuven, Kunsan, VUB, Imec)

A research consortium including Imec and KU Leuven has analysed the radiation response of dry-deposited metal-organic resists under extreme ultraviolet and electron-beam lithography. The study reveals distinct tone conversion behaviour depending on the exposure source employed during the patterning cycle. These findings offer useful insights for developing new resist chemistries required for advanced semiconductor manufacturing.

Semiconductors··Semiconductor Engineering

Silicon Photonic Modulator Reaches 200 Gb/s PAM4 With Reduced DSP (Science Tokyo, Yokohama, AIST, PETRA)

Researchers in Japan have created a low-voltage silicon photonic modulator that achieves 200 Gb/s PAM4 transmission while lowering digital signal processing overheads. The compact device integrates an electro-optic equaliser to support high-speed optical transceivers, catering to the increasing bandwidth requirements of artificial intelligence data centres.

Semiconductors··Semiconductor Engineering