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Self-Heating And Parasitics Challenge Multi-Tier CFET Scaling (TU Munich, IIT Kanpur)

Academic study highlights thermal and parasitic hurdles in multi-tier CFETs

By GPU Data Hub Desk · GPU Data Hub·Editorial standards·

Academics from the Technical University of Munich and IIT Kanpur have examined performance barriers facing multi-tier complementary field-effect transistors. Their study demonstrates that self-heating alongside parasitic interference from interconnect wiring presents major hurdles for vertically stacked nanosheet devices. These physical constraints could restrict the operational efficiency of future transistor architectures.

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This summary was written by the GPU Data Hub desk from reporting published by Semiconductor Engineering on 26 Oct 2026, 07:01. Read the full article at the original publisher.

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